Integrated circuits (ICs) are often very complex devices from both a structural and functional standpoint. The testing of such structurally and functionally complex devices is often equally complex. ICs are typically tested using sophisticated testing machines employing SPecific testing modes to ensure the functionality of the device. One test mode commonly used with memory chips, such as, for example, synchronous dynamic random access memory (SDRAM) chips, is test mode compression.
Test mode compression is a test mode that reduces the amount of time required to test the memory array or core of a memory chip. Generally, test mode compression condenses the test information from individual memory cells of a replaceable array section to a single bit that indicates whether that particular array section of memory cells passed or failed the functional test, and/or whether that array section is to be replaced by a redundant array section. Although the method of test mode compression reduces the amount of time required to test the memory array relative to directly reading and testing each individual memory cell separately or individually, testing an IC using test mode compression is still a relatively time consuming process.
The method of test mode compression conventionally stores the condensed data read from the memory array into a dedicated test mode compression register. The test mode compression register consumes valuable substrate space and adds complexity to the integrated circuit. Data in the test mode register is driven to an off-chip driver after a predetermined number of clock cycles, referred to as fixed latency. The depth of the test mode register fixes the latency period. The data in the test mode register is only driven to the off-chip driver at the expiration of the fixed latency period. Fixing the latency period also limits the maximum operational frequency at which the test can be administered. The depth of the register can be increased to increase the fixed latency period, thereby increasing the frequency at which the test can be administered. However, increasing the depth of the register consumes more valuable substrate space. Increasing the depth of the register also decreases the bandwidth, especially at lower operating frequencies.
Therefore, what is needed in the art is a method and apparatus for test mode compression that eliminates the need for a test mode compression register, thereby saving substrate space.
Furthermore, what is needed in the art is a method and apparatus for test mode compression that enables the latency period to be adjustable.
Moreover, what is needed in the art is a method and apparatus for test mode compression that enables testing at a higher frequency with a greater number of clock cycles between read operations.